The present invention relates to a synthesizer, and in particular a synthesizer with a lock detector, a lock algorithm, an extended range voltage controlled oscillator, and a simplified dual modulus divider.
Synthesizers are used in communication devices to obtain an output signal that is synchronized with some other signal, such as reference signal. Certain synthesizers use what is known as phase locked loop (PLL) with a voltage controlled oscillator (VCO) to cause the output signal frequency to vary in dependence upon the input control voltage. FIG. 1A illustrates a simple graph that shows that a desired output frequency can be caused to vary in linear dependence upon some control voltage Vc. As shown in this example, the output frequency has a range that varies by 100 MHz as the control voltage changes from 1.0 volts to 2.2 volts. Further, far from being ideal, there is typically only a narrow range A where the response is linear, with the response at each end of this range becoming increasingly nonlinear.
A PLL circuit 200 that uses a VCO to generate an output signal that is synchronized to a reference signal is illustrated in FIG. 2. PLL 200 includes a phase detector 220, a filter 230, a VCO 240, and a divide-by-N circuit 250. In operation, if the output of the VCO 240 is synchronized with the reference signal REF, then the signal generated by the divide-by-N circuit 250 will be in phase with the reference signal REF, thereby causing the output of the phase detector 220 to remain constant. As a result, since the output signal is synchronized with the reference signal (known as a xe2x80x9clockxe2x80x9d condition) the control voltage Vc that is input to the VCO 240 will remain the same. If, however, the output of the VCO is not in phase with the reference signal REF (known as a xe2x80x9cout of lockxe2x80x9d condition), the phase detector 220 will detect the amount that the VCO output is out of phase. The amount that the VCO output is out of phase will be used to correspondingly change the control voltage Vc, thereby causing the frequency of the signal output of the VCO to again become synchronized with the reference signal REF.
While the PLL circuit as described above is capable of automatically adjusting back to a lock condition, it is desirable to know whether the PLL circuit is in the lock condition or the out of lock condition at any moment in time. Accordingly, lock detectors are known that use the state of the PLL signals to indicate the presence or absence of a lock condition.
In many such conventional circuits, the phase detector, such as the phase detector 220 in FIG. 2, used can output both an xe2x80x9cUPxe2x80x9d signal and a xe2x80x9cDNxe2x80x9d (down) signal. If the PLL becomes out of lock, the UP and DN signals will no longer be balanced. Thus, if such a phase detector is used, complicated circuits that use both the UP and DN commands in order to determine if the PLL is in a lock condition or an out of lock condition are known. U.S. Pat. Nos. 5,969,576 and 5,126,690 are examples of such conventional circuits.
Nonetheless, a simplified lock detector circuit that can be easily implemented in digital logic and whose operation is independent from carrier frequency is desirable. The present invention, described hereinafter, provides such a circuit.
Furthermore, while FIG. 1A above illustrates the region in which the VCO will operate in terms of the relationship between the control voltage and the output frequency of a VCO that can be represented as a single characteristic curve, an extended range VCO can be configured to output different output frequencies for the same control voltage value, thus allowing the extended range VCO to operate in various regions. Each different region of operation can be achieved by changing the capacitive load associated with the extended range VCO, and thus obtaining a different characteristic curve. FIG. 1B illustrates an example of four characteristic curves C1, C2, C3, and C4 for an extended range VCO. In other words, by changing the load capacitance, a different characteristic curve results, thus extending the range of the VCO. While each of the curves corresponds to a different output frequency range, it is known that capacitor values can be chosen so that there is an overlap of the output frequency range among different curves. It is, however, difficult to choose which of the curves to use when using such an extended range VCO. The present invention, described hereinafter, provides such a methodology.
Further, in a conventional PLL, if one of the curves is currently being used with the VCO in a lock condition, and that lock condition is lost, an efficient, systematic method of determining the most appropriate curve to use to re-establish that lock condition does not exist.
Still furthermore, the divide-by-N circuit 250 described above with reference to FIG. 2 is typically implemented using two different counters. One such implementation of a divide-by-N circuit includes a program counter and a swallow counter. In typical implementations, both the program and swallow counters are clocked by or synchronized to the output of the previous block. As a result, the counters present capacitive loading, which limits the maximum operating speed of the divider.
It is an object of the present invention to provide a lock detect circuit, and in particular a lock detect circuit that is efficient at MegaHertz reference frequencies and GigaHertz carrier frequencies.
It is another object of the present invention to provide a method of and apparatus for generating a lock detect signal.
It is another object of the present invention to provide a method to systematically obtain a lock condition, including the ability to reacquire lock after a lock condition has existed, and then the lock condition is lost.
It is a further object of the present invention to provide a PLL with a divide-by-N circuit that uses only a single counter and a decoder.
It is a further object of the present invention to provide method of using a divide-by-N circuit that uses only a single counter and different decoders to design different PLLs that have different frequency and/or channel characteristics.
The present invention attains at least the above objects, and others, either singly or in combination by providing a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.
According to one aspect, the present invention provides an apparatus for and a method of generating a lock detect signal indicative of stability of a frequency of an output signal based upon UP and DN signals received from a phase detector. In the apparatus and method, the UP and DN signals are combined, and then delayed, so that the delayed and undelayed combined signals can be operated upon to obtain the lock detect signal.
According to another aspect, the present invention provides a method of establishing a lock condition with a voltage controlled oscillator in which the voltage controlled oscillator can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions. Each characteristic curve has a different capacitance value associated therewith and a lock is established with one of the plurality of characteristic curves the characteristic curve that is used is one that is chosen to minimize phase noise.
According to another aspect, the present invention provides a method of reestablishing a lock condition in a synthesizer having an extended range voltage controlled oscillator. The extended range voltage controlled oscillator can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions. Each characteristic curve has a different capacitance value associated therewith.
According to yet another aspect, the present invention provides a divide circuit implemented using only a single counter along with a decoder, as well as a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.
Advantages of each of the above-recited aspects of the present invention will become apparent in the discussion provided hereinafter.